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a
FEATURES Low Power: 300 mW On-Chip T/H, Reference Single +5 V Power Supply Operation Selectable 5 V or 3 V Logic I/O Wide Dynamic Performance APPLICATIONS Digital Communications Professional Video Medical Imaging Instrumentation
AINB AIN +5V +5V
9-Bit, 30 MSPS ADC AD9049
FUNCTIONAL BLOCK DIAGRAM
GND
AD9049
T/H
REFERENCE CKTS
ADC DECODE LOGIC 9
SUM AMP ENCODE TIMING
DAC
ADC
PRODUCT DESCRIPTION
+5V
The AD9049 is a complete 9-bit monolithic sampling analogto-digital converter (ADC) with an onboard track-and-hold and reference. The unit is designed for low cost, high performance applications and requires only +5 V and an encode clock to achieve 30 MSPS sample rates with 9-bit resolution. The encode clock is TTL compatible and the digital outputs are CMOS; both can operate with 5 V/3 V logic, selected by the user. The two-step architecture used in the AD9049 is optimized to provide the best dynamic performance available while maintaining low power consumption. A 2.5 V reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. Fabricated on an advanced BiCMOS process, the AD9049 is packaged in space saving surface mount packages (SOIC, SSOP) and is specified over the industrial (-40C to +85C) temperature range.
AIN (+3.3V 0.512V) 0.1F +5V 0.1F
3 10 5
4
2, 8, 11, 20, 22
9 BITS
AD9049
6
(2)
74AC574
0.1F 9 13 1, 7, 12, 21, 23
ENCODE
Figure 1. Typical Connections
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
AD9049-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V , V
D DD
= +5 V; internal reference; ENCODE = 30 MSPS unless otherwise noted)
Test Level Min AD9049BR/BRS Typ Max 9 Units Bits LSB LSB LSB LSB % FS ppm/C V p-p mV mV k pF MHz V ppm/C MSPS MSPS ns ps, rms ns ns ns ENOBs ENOBs dB dB
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error Gain Tempco1 ANALOG INPUT Input Voltage Range Input Offset Voltage Input Resistance Input Capacitance Analog Bandwidth BANDGAP REFERENCE Output Voltage Temperature Coefficient1 SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Propagation Delay (tPD)2 DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time ENOBS fIN = 2.3 MHz fIN = 10.3 MHz Signal-to-Noise Ratio (SINAD)3 fIN = 2.3 MHz fIN = 10.3 MHz Signal-to-Noise Ratio (Without Harmonics) fIN = 2.3 MHz fIN = 10.3 MHz 2nd Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz 3rd Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz Two-Tone Intermodulation Distortion (IMD)4 Differential Phase Differential Gain
Temp
+25C Full +25C Full Full +25C Full +25C +25C Full +25C +25C +25C +25C Full +25C +25C +25C +25C Full +25C +25C +25C +25C +25C +25C
I V I V IV I V V I IV I V V I V I IV V V IV V V V I V I
0.5 1.0 0.5 0.5 1.0 0.5 GUARANTEED 1.0 7.5 100 1.024 +7 5.0 5 100 2.5 50
-10 -32 3.5
+25 +51 6.5
2.4
2.6
30 1.5 2.7 5 5 10 10 8.56 8.51 53.3 53 3
15
8.01
50
+25C +25C +25C +25C +25C +25C +25C +25C +25C
V I V I V I V V V
51
53.5 53.3 -69 -67 -75 -66 65 0.15 0.35
dB dB dBc dBc dBc dBc dBc Degrees %
-60
-58
-2-
REV. A
AD9049
Parameter ENCODE INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL) DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Voltage (3.0 VDD) Logic "0" Voltage (3.0 VDD) Output Coding POWER SUPPLY VD, VDD Supply Current5 Power Dissipation5 Power Supply Rejection Ratio (PSRR)6 Temp Full Full Full Full +25C +25C +25C Full Full Full Full Test Level IV IV IV IV V IV IV IV IV IV IV Min 2.0 0.8 1 1 10 10 10 4.95 0.05 2.95 Offset Full Full +25C IV IV I 40 Binary 60 300 0.05 Code 80 400 10 166 166 AD9049BR/BRS Typ Max Units V V A A pF ns ns V V V V
mA mW mV/V
NOTES 1 "Gain Tempco" is for converter only; "Temperature Coefficient" is for bandgap reference only. 2 Output propagation delay (t PD) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF maximum loads. 3 RMS signal to rms noise with analog input signal 0.5 dB below full scale at specified frequency. 4 Intermodulation measured relative to either tone with analog input frequencies of 9.5 MHz and 9.9 MHz at 7 dB below full scale. 5 Power dissipation is measured at 30 MSPS with AIN of 10.3 MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at other conditions. 6 Measured as the ratio of the change in offset voltage for 5% change in +V D. Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
ABSOLUTE MAXIMUM RATINGS*
Test Level I - 100% Production Tested. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only.
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V ANALOG IN . . . . . . . . . . . . . . . . . . . . . . -1.0 V to VD + 1.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature AD9049BR/BRS . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
ORDERING GUIDE
Model AD9049BR AD9049BRS
Temperature Range -40C to +85C -40C to +85C
Package Option* R-28 RS-28
*R = Small Outline (SO); RS = Shrink Small Outline (SSOP).
REV. A
-3-
AD9049
Table I. AD9049 Digital Coding (Single Ended Input AIN, AINB Bypassed to GND)
Analog Input 3.810 3.300 2.790
Voltage Level Positive Full Scale Midscale Negative Full Scale
PIN DESCRIPTIONS
Digital Output MSB . . . LSB Digital Output 111111111 011111111 000000000
Pin No 1, 7, 12, 21, 23 2, 8, 11 3 4 5 6 9 10 13 14 15 16-19 20, 22 24-26 27 28
Name GND VD VREFOUT VREFIN COMP REFBP AINB AIN ENCODE NC D8 (MSB) D7-D4 VDD D3-D1 D0 (LSB) NC
Function Ground. Analog +5 V 5% power supply. Internal bandgap voltage reference (nominally +2.5 V). Input to reference amplifier. Voltage reference for ADC is connected here. Internal compensation pin, 0.1 F bypass connected here to VD (+5 V). External connection for (0.1 F) reference bypass capacitor. Complementary analog input pin (Analog input bar). Analog input pin. Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding) on rising edge of encode signal. Not internally connected. Most significant bit of ADC output. Digital output bits of ADC. Digital output power supply (only used by digital outputs). Digital output bits of ADC. Least significant bit of ADC output. Not internally connected.
PIN CONNECTIONS
GND 1 VD 2 VREFOUT 3 VREFIN 4 COMP 5 REFBP 6 GND 7
28 NC 27 D0 (LSB) 26 D1 25 D2 24 D3 23 GND
22 VDD TOP VIEW VD 8 (Not to Scale) 21 GND 20 VDD 19 D4 18 D5 17 D6 16 D7 15 D8 (MSB)
AD9049
AINB 9 AIN 10 VD 11 GND 12 ENCODE 13 NC 14
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9049 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD9049
N N+1 N+2 N+3 N+4 N+5 AIN MIN TYP 2.7ns 10ns 10ns 5.0ns 8.2ns 166ns 166ns 15.0ns MAX
tA
ENCODE
tA tEH tEL tPD
N-4 N-3 N-2 N-1 N
APERTURE DELAY PULSE WIDTH HIGH PULSE WIDTH LOW OUTPUT PROP DELAY
tEH
tEL tPD
DIGITAL OUTPUTS
N-5
Figure 2. Timing Diagram
VD
VDD (Pins 20, 22) +3V to +5V 8k 8k INPUT BUFFER D0-D8 ENCODE (Pin 13)
VD
AINB (Pin 9) AIN (Pin 10) 16k 16k
Analog Input
VD
Output Stage
VD
Encode Input
VREFOUT (Pin 3)
AV VREFIN (Pin 4) VREFBF (Pin 6)
VREF Output
Reference Circuit Figure 3. Equivalent Circuits
REV. A
-5-
AD9049-Typical Performance Curves
361 342 AIN = 10.3 MHz 58 57 323
DISSIPATION - mW
304 285 266 247 OUTPUTS @ 3V 228 209 190 171 0 10 20 CLOCK RATE - MSPS 30 OUTPUTS @ 5V
SIGNAL-TO-NOISE RATIO - dB (SINAD)
56 55 54 53 52 51 50 49 48 -40 0 20
ENCODE = 30 MSPS AIN = 10.3 MHz
- 20
40
60
80
90
TEMPERATURE - C
Figure 4. Power Dissipation vs. Clock Rate
Figure 7. SNR vs. Temperature
80 ENCODE = 30 MSPS 74 HARMONIC DISTORTION 68
0 -10 -20 -30 -40 ENCODE = 30 MSPS f1 IN = 9.5 MHz @ -7 dBFS f2 IN = 9.9 MHz @ -7 dBFS 2f1-f2 = -65.4 dBc 2f2-f1 = -65.0 dBc
62
dB dB
-50
SIGNAL-TO-NOISE 56
-60 -70 -80
50
-90 -100 -110
44 38 1 10 ANALOG INPUT FREQUENCY - MHz 100
-120 0 2.5 5 7.5 10 FREQUENCY - MHz 12.5 15
Figure 5. SNR/Distortion vs. Frequency
Figure 8. Two-Tone IMD
60
0.50
DIFF GAIN - %
58
0.25 0.00 -0.25 -0.50
SIGNAL-TO-NOISE RATIO - dB (SINAD)
AIN = 10.3 MHz 56
54
1
2
3
4
5
6
DIFF PHASE - Degrees
52 50
0.50 0.25 0.00 -0.25 -0.50 1 2 3 4 5 6
48 46 0 5 10 15 20 CLOCK RATE - MSPS 25 30
Figure 6. SNR vs. Clock Rate
Figure 9. Differential Gain/Differential Phase
-6-
REV. A
AD9049
0 -10 -20 -30 -40 -50 dB -60 -70 -80 -90 -100 -110 -120 0 2.5 5 7.5 10 FREQUENCY - MHz 12.5 15
51.0 25 30 35 40 45 50 55 60 65 70 75 55.0
SIGNAL-TO-NOISE - dB (SINAD)
ENCODE = 30 MSPS ANALOG IN = 2.3 MHz SNR = 53.0 dB SNR (W/O HAR) = 53.3 dB 2ND HARMONIC = 69.3 dB 3RD HARMONIC = 72.9 dB
54.5 54.0 53.5 53.0 52.5 52.0 51.5
ENCODE = 30 MSPS AIN = 2.3 MHz
DUTY CYCLE - %
Figure 10. FFT Plot 30 MSPS, 2.3 MHz
Figure 13. SNR vs. Clock Pulse Width
0 -10 -20 -30 -40 -50
dB
1.0
ENCODE = 30 MSPS ANALOG IN = 4.3 MHz SNR = 53.0 dB SNR (W/O HAR) = 53.3 dB 2ND HARMONIC = 69.0 dB 3RD HARMONIC = 72.6 dB
0.5 ENCODE = 30 MSPS 0.0 -0.5
ADC GAIN - dB
-1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5
-60 -70 -80 -90 -100 -110 -120 0 2.5 5 7.5 10 FREQUENCY - MHz 12.5 15
1
10
100
1000
ANALOG INPUT FREQUENCY - MHz
Figure 11. FFT Plot 30 MSPS, 4.3 MHz
Figure 14. ADC Gain vs. AIN Frequency
0 -10 -20 -30 -40 -50
tPD - ns dB
15.0
ENCODE = 30 MSPS ANALOG IN = 10.3 MHz SNR = 52.7 dB SNR (W/O HAR) = 53.1 dB 2ND HARMONIC = 66.4 dB 3RD HARMONIC = 70.5 dB
14.0 13.0 12.0
[1] - 5V DATA RISING EDGE [2] - 5V DATA FALLING EDGE [3] - 3V DATA RISING EDGE [4] - 3V DATA FALLING EDGE
[3] [1]
11.0 [4] 10.0 9.0 8.0 7.0 6.0 5.0 - 40 -20 0 20 40 60 80 100 [2]
-60 -70 -80 -90 -100 -110 -120 0 2.5 5 7.5 10 FREQUENCY - MHz 12.5 15
TEMPERATURE - C
Figure 12. FFT Plot 30 MSPS, 10.3 MHz
Figure 15. tPD vs. Temperature 3 V/5 V
REV. A
-7-
AD9049
THEORY OF OPERATION
1k +5V 1k VIN -0.5V to +0.5V 10
Refer to the block diagram on the front page. The AD9049 employs a subranging architecture with digital error correction. This combination of design techniques ensures true 9-bit accuracy at the digital outputs of the converter. At the input, the analog signal is buffered by a high speed differential buffer and applied to a track-and-hold (T/H) that holds the analog value which is present when the unit is strobed with an ENCODE command. The conversion process begins on the rising edge of this pulse. The two stage architecture completes a coarse and then a fine conversion of the T/H output signal. Error correction and decode logic correct and align data from the two conversions and present the result as a 9-bit parallel digital word. Output data are strobed on the rising edge of the ENCODE command. The subranging architecture results in five pipeline delays for the output data. Refer to the AD9049 Timing Diagram.
USING THE AD9049 3 V System
+5V
AD8041
9 0.1F 1k +5V 1k AD820
AD9049
0.1F
Figure 16. Single Supply, Single Ended, DC Coupled AD9049
1k +5V 1k VIN -0.5V to +0.5V 0.1F 10
+5V
AD8011
-5V 0.1F 9
AD9049
The digital input and outputs of the AD9049 can easily be configured to directly interface to 3 V logic systems. The encode input (Pin 13) is TTL compatible with a logic threshold of 1.5 V. This input is actually a CMOS stage (refer to Equivalent Encode Input Stage) with a TTL threshold, allowing operation with TTL, CMOS and 3 V CMOS logic families. Using 3 V CMOS logic allows the user to drive the encode directly without the need to translate to +5 V. This saves the user power and board space. As with all high speed data converters, the clock signal must be clean and jitter free to prevent the degradation of dynamic performance. The AD9049 outputs can also directly interface to 3 V logic systems. The digital outputs are standard CMOS stages (refer to AD9049 Output Stage) with isolated supply pins (Pins 20, 22 VDD). By varying the voltage on the VDD pins, the digital output levels vary respectively. By connecting Pins 20 and 22 to the 3 V logic supply, the AD9049 will supply 3 V output levels. Care should be taken to filter and isolate the output supply of the AD9049 as noise could be coupled into the ADC, limiting performance.
Analog Input
Figure 17. Single Ended, Capacitively Coupled AD9049
1k +5V 1k VIN -0.5V to +0.5V 0.1F T1-1T 10
+5V
AD8011 50
-5V 9
AD9049
Figure 18. Differentially Driven AD9049 Using Transformer Coupling.
The AD830 provides a unique method of providing dc level shift for the analog input. Using the AD830 allows a great deal of flexibility for adjusting offset and gain. Figure 19 shows the AD830 configured to drive the AD9049. The offset is provided by the internal biasing of the AD9049 differential input (Pin 9). For more information regarding the AD830, see the AD830 data sheet.
VIN -0.5V to +0.5V 1 2 3 AD830 4 -5V 9 +15V 7 10 +5V
The analog input of the AD9049 is a differential input buffer (refer to AD9049 Equivalent Analog Input). The differential inputs are internally biased at +3.3 V, obviating the need for external biasing. Excellent performance is achieved whether the analog inputs are driven single-ended or differential. (For best dynamic performance, impedances at AIN and AINB should match.) Figure 16 shows typical connections for the analog inputs when using the AD9049 in a dc coupled system with single ended signals. All components are powered from a single +5 V supply. The AD820 is used to offset the ground referenced input signal to the level required by the AD9049. AC coupling of the analog inputs to the AD9049 is easily accomplished. Figure 17 shows capacitive coupling of a single ended signal while Figure 18 shows transformer coupling differentially into the AD9049.
AD9049
0.1F
Figure 19. Level Shifting with the AD830
-8-
REV. A
AD9049
Overdrive of the Analog Input Power Dissipation
Special care was taken in the design of the analog input section of the AD9049 to prevent damage and corruption of data when the input is overdriven. The nominal input range is +2.788 V to 3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range comparators detect when the analog input signal is out of this range and shut the T/H off. The digital outputs are locked at their maximum or minimum value (i.e., all "0" or all "1"). This precludes the digital outputs from changing to an invalid value when the analog input is out of range. When the analog input signal returns to the nominal range, the out-of-range comparators switch the T/H back to the active mode and the device recovers in approximately 10 ns. The input is protected to one volt outside the power supply rails. For nominal power (+5 V and ground), the analog input will not be damaged with signals from +6.0 V to -1.0 V.
Timing
The power dissipation specification in the parameter table is measured under the following conditions: encode is 30 MSPS, analog input is -1 dBFS at 10.3 MHz, the digital outputs are loaded with approximately 7 pF (10 pF maximum), and VDD is 5 V. These conditions intend to reflect actual usage of the device. As shown in Figure 4, the actual power dissipation varies based on these conditions. For instance, reducing the clock rate will reduce power as expected for CMOS type devices. Also the loading determines the power dissipated in the output stages. From an ac standpoint, the capacitive loading will be the key (refer to Equivalent Output Stage). The analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. Power dissipation increases as more data bits switch at faster rates. For instance, if the input is a dc signal that is out of range, no output bits will switch. This minimizes power in the output stages but is not realistic from a usage standpoint. The dissipation in the output stages can be minimized by interfacing the outputs to 3 V logic (refer to USING THE AD9049, 3 V System). The lower output swings minimize consumption. Refer to Figure 4 for performance characteristics.
Voltage Reference
The performance of the AD9049 is very insensitive to the duty cycle of the clock. Pulse width variations of as much as 10% will cause no degradation in performance (see Figure 13, SNR vs. Clock Pulse Width). The AD9049 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (refer to the AD9049 Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9049; these transients can detract from the converter's dynamic performance. The minimum guaranteed conversion rate of the AD9049 is 3 MSPS. Below a nominal of 1.5 MSPS the internal T/H switches to a track function only. This precludes the T/H from drooping to the rail during the conversion process and minimizes saturation issues. At clock rates below 3 MSPS dynamic performance degrades. The AD9049 will operate in burst mode operation, but the user must flush the internal pipeline each time the clock stops. This requires 5 clock pulses each time the clock is restarted for the first valid data output (refer to Figure 2 Timing Diagram).
A stable and accurate +2.5 V voltage reference is built into the AD9049 (Pin 3, VREF Output). In normal operation the internal reference is used by strapping Pins 3 and 4 of the AD9049 together. The internal reference has 500 A of extra drive current that can be used for other circuits. Some applications may require greater accuracy, improved temperature performance or adjustment of the gain of the AD9049, which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can be used to connect to Pin 4 of the AD9049. The VREFIN requires 5 A of drive current. The input range can be adjusted by varying the reference voltage applied to the AD9049. No appreciable degradation in performance occurs when the reference is adjusted 5%. The full-scale range of the ADC tracks reference voltage changes linearly.
REV. A
-9-
AD9049
Figure 20. Evaluation Board Top Layer
Figure 22. Evaluation Board Bottom Layer
Figure 21. Evaluation Board Ground Layer
-10-
REV. A
AD9049
U3 74AC574R U1 AD9049R
R5 1k 3 4 5 6 9 10 13 D8/MSB D7 D6 D5 D4 D3 D2 D1 D0 NC +5V +5V 15 16 17 18 19 24 25 26 27 20 22 9 8 7 6 5 4 3 2 8D 7D 6D 5D 4D 3D 2D 1D CK 11 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19
R4 1k J2 R3 50
2
U2 AD9631Q
TP3 C9 0.1F
IN 6 OUT 3 IN
VREFOUT VREFIN COMP REFBP AINB AIN ENC
J3 HDR20
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +5V
U6:B 74AC00R
4 5 J7 6
C1 0.1F C2 0.1F C3 0.1F E1 +5V +5V
TP2 9 8 7 6 5 4 3 2
U4 74AC574R
8D 7D 6D 5D 4D 3D 2D 1D CK 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19
R1 50 4 +5V
3 OUT VCC Y1 GND 2
SW41 U6:A 74AC00R
11 1 2 3
11
12 13
U6:D 74AC00R
J6 +5V
R2 2k
9 10
8
U6:C 74AC00R
J1 C5 10F + +5V C7 0.1F +5V C10 0.1F C12 0.1F C13 0.1F C14 0.1F C15 0.1F C16 0.1F C17 0.1F C22 0.1F C23 0.1F C24 0.1F
J5 -5.2V C6 10F + C8 0.1F -5.2V C20 0.1F
Figure 23. Evaluation Board Schematic
REV. A
-11-
AD9049
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SOIC (R-28)
0.7125 (18.10) 0.6969 (17.70)
29 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
28-Lead SSOP (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
0.311 (7.9) 0.301 (7.64)
1
14
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
0.015 (0.38) 0.010 (0.25)
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
8 0
0.03 (0.762) 0.022 (0.558)
-12-
REV. A
PRINTED IN U.S.A.
C2104a-2-12/96

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